The invention relates to a printed circuit board tester.
The invention is based on prior art according to EP 875 767 A2 which was published by the applicant of the present patent application, disclosing a test fixture comprising a plurality of test connections, in which circuit board test points of the board under test are in contact with a test connection via an electrical connection.
The electronic analyzer is electrically connected to a grid pattern on which an adapter and/or a translator is mounted on which a circuit board to be tested may be placed. The adapter and/or translator produces an electrical contact from the circuit board test points of the board under test to contact points of the grid pattern.
This test fixture is characterized by at least two contact points being electrically connected to each other. More particularly, in this tester several contact points in each case are electrically connected to each other along a straight-line scanning channel in each case. The individual scanning channels are electrically connected to an electronic analyzer. Since each scanning channel is connected to several contact points the number of units of the electronic analyzer as compared to an electronic analyzer of a comparable tester is considerably reduced and the overall configuration of the test fixture becomes very simple.
Although in this test fixture several test points are electrically connected to a single scanning channel, it has been found out surprisingly that in by far the majority of applications no double assignments of the scanning channels occur or that any such double assignments may be reliably obviated by dictating the assignment of the circuit board test points to the contact points of the test fixture. This is achieved by the known tester creating a high contact point density by relatively uncomplicated means, requiring for instance an average spacing of 800 xcexcm or less between adjacent contact points. This high circuit board test point density is of advantage since it permits contacting a correspondingly high local circuit board test point density whilst, at the same time, making a sufficient redundancy available due to the contact point density thus enabling a double assignment of a scapning channel to be reliably avoided.
The object of the present invention is to provide a simple and low-cost tester for testing large-area circuit boards such as, for instance, backplanes sized e.g. 1000 mmxc3x97750 mm. Large-area circuit boards in the sense of the invention are circuit boards sized at least 500 mmxc3x97500 mm, i.e. having a surface area of at least 250,000 mm2.
This object is achieved by a printed circuit board tester having the features as they read from claim 1. Advantageous aspects read from the sub-claims.